1. Field of the Invention
The present invention relates to a switching regulator, and more particularly, to a switching regulator for fixing a frequency by controlling a constant-time trigger.
2. Description of the Prior Art
Regulators usually include switching regulators and liner regulators. The characteristics of liner regulators are that they are cheap, easy to use and respond quickly. However the efficiency of liner regulators is poor, often consuming 50% of the power. Although a switching regulator has slow response, its power efficiency is great. Power consumption plays an important role in circuit design nowadays. As for a quick response requirement, switching regulators utilize a constant-time trigger to substitute for an error amplifier with additional frequency compensation elements used for controlling signal differences between PWM loops. The constant-time trigger is used for triggering a fixed on time or a fixed off time to control the whole switching regulator.
Please refer to FIG. 1. FIG. 1 is a diagram of a switching regulator 10 according to the prior art. The switching regulator 10 includes a power stage 12, an output capacitor Cout, a loading Rload, a reference voltage generator 14, a comparator 15, and a constant-time trigger 16. The power stage 12 includes a first switch SW1, a second switch SW2, an inverter 17, and an output inductor Lout. The second switch SW2 is coupled to the first switch SW1. The output inductor Lout is coupled to the first switch SW1 and the second switch SW2. The inverter 17 is coupled to the constant-time trigger 16 and a control end 104 of the second switch SW2 for processing an inverse operation on a signal outputted from the constant-time trigger 16. The output capacitor Cout is coupled to the output inductor Lout with an output voltage Vout across the capacitor. The output capacitor Cout further includes an equivalent series resistance ESR. The reference voltage generator 14 is used for generating a reference voltage Vref. The comparator 15 includes a first input end 152 coupled to the output inductor Lout and the output capacitor Cout for receiving a feedback voltage VFB (equals the output voltage Vout). The comparator 15 includes a second input end 154 coupled to the reference voltage generator 14. The constant-time trigger 16 is coupled to the comparator 15 and the power stage 12. The constant-time trigger 16 is used for controlling turning on and off the first switch SW1 and the second switch SW2 of the power stage 12 according to a result of the comparator 15. An input end 122 of the first switch SW1 is coupled to an input voltage terminal Vin, and an input end 124 of the second switch SW2 is coupled to ground. The comparator 15 is an error comparator. The first switch SW1 and the second switch SW2 are metal-oxide semiconductor transistors (MOS). When the constant-time trigger 16 is an on-time trigger, it is used for controlling on time of the first switch SW1 and the second switch SW2. When the constant-time trigger 16 is an off-time trigger, it is used for controlling off time of the first switch SW1 and the second switch SW2.
Please refer to FIG. 2 and FIG. 1. FIG. 2 is a diagram illustrating signal waveforms in FIG. 1. The upper waveform is a variation of an inductor current IL in time, where it rises in a positive slope for a span and drops in a negative slope for a span. Due to the output voltage Vout equaling the feedback voltage VFB, the feedback voltage VFB could be represented as the product of the inductor current IL and the equivalent series resistance ESR. Assume that the constant-time trigger 16 is an on time trigger for controlling turning on the first switch SW1 for a fixed time TON. The comparator 15 is used for comparing the feedback voltage VFB and the reference voltage Vref. When the feedback voltage VFB is lower than the reference voltage Vref, the comparator 15 triggers a high level signal to the constant-time trigger 16. The constant-time trigger 16 controls the first switch SW1 to turn on for the fixed time TON and to turn off the first switch SW1 for a fixed time TOFF. The constant-time trigger 16 turns on the second switch SW2 to form a loop.
Please continue to refer to FIG. 1 and FIG. 2. Assume that the constant-time trigger 16 is an on-time trigger. The on-time of the first switch SW1 is TON and the off-time of the first switch SW1 is TOFF. A switching frequency f1 of the switching regulator 10 can be represented as the following equation: f1=Vout/TON(Vin−IL×RDSON), where TON is the on-time of the first switch SW1, IL is the inductor current, and RDSON is the resistor of the switch when conducting. Thus, the frequency f1 relates to the output voltage Vout, the input voltage Vin and the resistor RDSON.
Fixing frequency applications of switching regulators are already disclosed in U.S. Pat. No. 6,774,611 “Circuits and Methods for Synchronizing Non-constant Frequency Switching Regulators with A Phase Locked Loop”, U.S. Pat. No. 6,885,175 “Fixed Frequency Hysteretic Regulator”, and U.S. Pat. No. 6,456,050 “Virtual Frequency-Controlled Switching Voltage Regulator”. In U.S. Pat. No. 6,774,611, the method of work is adjusting the on-time TON and the off-time TOFF by a phase difference generated by a phase-locked loop (PLL).
In U.S. Pat. No. 6,885,175, the main application is aimed at a hysteresis system. Please refer to FIG. 3 that is a diagram of a hysteresis system 30 according to the prior art. The upper limit of the hysteresis system 30 is a first reference voltage Vref1 , and the lower limit of the hysteresis system 30 is a second reference voltage Vref2. A comparator 35 is used for comparing the first reference voltage Vref1 with a feedback voltage VFB, and a comparator 36 is used for comparing the second reference voltage Vref2 with the feedback voltage VFB. The magnitude of the first reference voltage Vref1 and the magnitude of the second reference voltage Vref2 are controlled by an offset generator 32 which is controlled by a frequency f2 of the hysteresis system 30. When the frequency f2 of the hysteresis system 30 is too large, the offset generator 32 outputs the offsets Offset1 and Offset2 with a greater value. When the frequency f2 of the hysteresis system 30 is too small, the offset generator 32 outputs the offsets Offset1 and Offset2 with a smaller value. The hysteresis system 30 includes an adder 33 and a subtractor 34. The adder 33 is used for adding a reference voltage Vref and the offset Offset1 together to get the first reference voltage Vref1. The subtractor 34 is used for subtract the offset Offset2 from the reference voltage Vref to get the second reference voltage Vref2. Frequency fixing is achieved by utilizing the offset generator 32 to adjust the magnitude of the offsets Offset1 and Offset2.
In U.S. Pat. No. 6,456,050, the method of work is adding a feedback mechanism to the system. The off-time TOFF is adjusted by variations of current indirectly. Thus a frequency of the system is changed.
Due to the frequency f1 of the switching regulator 10 being relating to the output voltage Vout and the input voltage Vin, a different output voltage Vout and a different input voltage Vin leads to a different frequency f1 even though the on-time TON is equal. The frequency f1 changes with variations of the output voltage Vout and the input voltage Vin. Therefore, the frequency of the system is unstable.